pat gelsinger (@PGelsinger) designed chips at intel in a period when doing so could involve writing your own hardware description language, which he did for the 486. his team also built a compiler and tools for automating placement and routing. “I wrote my own language,” he says in this pod with @RaghuRaghuram and @appenz. it's a good reminder of how many things had to be invented alongside the processors themselves, and why the prospect of AI taking over more of that work is so exciting.
pat then asks us to imagine designing an excellent AI accelerator in three months. getting it fabricated, packaged, and into a working rack takes roughly nine more in his example (the relevant unit is now the rack: “nothing's a chip anymore, it's a rack”). so there's a period in which your very clever design has to sit and wait for its physical existence, while the models whose workloads you've designed it for can keep evolving. his description of graphcore is that it “wasn't a bad design, but the world moved on.” i think about how often people announce a new model or a new way of using one, and nine months seems like a very long commitment to your current understanding of what the hardware ought to do.
guido's argument is that agents should make it easier to support a greater variety of architectures, because writing all the software to use an unfamiliar chip has historically been one of the barriers. pat's answer is that somebody still has to pay for manufacturing and for a place to put all these chips. he expects consolidation, even with better software tools. if you're a customer committing to a data center and its electricity supply, you're making a rather different bet than the engineer who's just got a new design to work.
which leaves a lot for hardware people to do. pat is especially dissatisfied with hbm (high-bandwidth memory), pointing to problems with density, bandwidth, and heat; he calls it “a hideous memory,” and says he's just funded a new memory company that's still in stealth. he wants better memory closer to compute, optical connections between systems, and less electricity lost in conversion on its way to the chip. he also seems very happy to talk about cooling. “engineers are becoming plumbers,” is how he puts it.
if we're excited about being able to design more things with AI, we should be excited about the work that allows us to manufacture and operate them, too. pat has already lived through a period of having to invent quite a lot of the surrounding machinery. it makes sense that he'd see another one as an opportunity.
pat then asks us to imagine designing an excellent AI accelerator in three months. getting it fabricated, packaged, and into a working rack takes roughly nine more in his example (the relevant unit is now the rack: “nothing's a chip anymore, it's a rack”). so there's a period in which your very clever design has to sit and wait for its physical existence, while the models whose workloads you've designed it for can keep evolving. his description of graphcore is that it “wasn't a bad design, but the world moved on.” i think about how often people announce a new model or a new way of using one, and nine months seems like a very long commitment to your current understanding of what the hardware ought to do.
guido's argument is that agents should make it easier to support a greater variety of architectures, because writing all the software to use an unfamiliar chip has historically been one of the barriers. pat's answer is that somebody still has to pay for manufacturing and for a place to put all these chips. he expects consolidation, even with better software tools. if you're a customer committing to a data center and its electricity supply, you're making a rather different bet than the engineer who's just got a new design to work.
which leaves a lot for hardware people to do. pat is especially dissatisfied with hbm (high-bandwidth memory), pointing to problems with density, bandwidth, and heat; he calls it “a hideous memory,” and says he's just funded a new memory company that's still in stealth. he wants better memory closer to compute, optical connections between systems, and less electricity lost in conversion on its way to the chip. he also seems very happy to talk about cooling. “engineers are becoming plumbers,” is how he puts it.
if we're excited about being able to design more things with AI, we should be excited about the work that allows us to manufacture and operate them, too. pat has already lived through a period of having to invent quite a lot of the surrounding machinery. it makes sense that he'd see another one as an opportunity.
a16z@a16z · Oct 9Former Intel CEO Pat Gelsinger with a16z's Raghu Raghuram and Guido Appenzeller on the next wave of semiconductor innovation and the physical constraints shaping the AI buildout:
Drawing on his experience designing Intel's 386 and 486 processors, Pat explains how AI could transform chip design, but also why faster design alone won't solve the industry's biggest problems.
They examine the bottlenecks in manufacturing, memory bandwidth, advanced packaging, and power, and why today's explosion of specialized AI chips may eventually consolidate around a smaller number of architectures.
They also discuss the potential for new memory technologies, the shift from copper to optical networking, and why energy capacity could become a major constraint on AI growth.
Finally, they revisit Pat's VMware years to ask what virtualization might look like when infrastructure is built for agents rather than humans.
YouTube: youtu.be/1Q_7yU7FZ1k
1:05 Hired by Intel at 18
3:50 Arguing with Stanford professors
7:25 Will AI design the next gen chips?
8:45 Designing faster than fabs can build
11:55 Why GPUs are stuck with bad memory
13:40 Why 100 AI chips will collapse to a few
19:15 Agents make new chips cheap to run
22:10 No new memory chip since the 90s
27:20 Why 16-layer chip stacks are a fantasy
32:15 The physics that keeps memory next to compute
34:55 "I declared the death of copper"
38:05 AI traffic breaks the internet's design
42:40 "Energy capacity equals economic capacity"
46:25 The 130-year-old power war AI reopened
48:50 VMware for agents
@PGelsinger @RaghuRaghuram @appenz
Drawing on his experience designing Intel's 386 and 486 processors, Pat explains how AI could transform chip design, but also why faster design alone won't solve the industry's biggest problems.
They examine the bottlenecks in manufacturing, memory bandwidth, advanced packaging, and power, and why today's explosion of specialized AI chips may eventually consolidate around a smaller number of architectures.
They also discuss the potential for new memory technologies, the shift from copper to optical networking, and why energy capacity could become a major constraint on AI growth.
Finally, they revisit Pat's VMware years to ask what virtualization might look like when infrastructure is built for agents rather than humans.
YouTube: youtu.be/1Q_7yU7FZ1k
1:05 Hired by Intel at 18
3:50 Arguing with Stanford professors
7:25 Will AI design the next gen chips?
8:45 Designing faster than fabs can build
11:55 Why GPUs are stuck with bad memory
13:40 Why 100 AI chips will collapse to a few
19:15 Agents make new chips cheap to run
22:10 No new memory chip since the 90s
27:20 Why 16-layer chip stacks are a fantasy
32:15 The physics that keeps memory next to compute
34:55 "I declared the death of copper"
38:05 AI traffic breaks the internet's design
42:40 "Energy capacity equals economic capacity"
46:25 The 130-year-old power war AI reopened
48:50 VMware for agents
@PGelsinger @RaghuRaghuram @appenz
3 3 0 24 4.8K 8
Antonio García Martínez (agm.eth)
Erik Torenberg
Luke Metro
Gabriel Vasquez